Presenter

Mr. Antonio De La Piedra

Abstract

Typically, sensor nodes are constrained by size and energy consumption. Reducing the energy consumption of the network by decreasing the bandwidth
is possible by rising the amount of processing performed in the node. However, the low-power microcontrollers generally utilized in commercial nodes require too much time for executing complex algorithms. Consequently, the energy consumption is higher than using a separate accelerator that can be switched on and off when required.

In this thesis, two alternative architectures for sensor node construction are proposed. The first one is based on the combination of low-power microcontrollers and Field-Programmable Gate Arrays (FPGAs) whereas the second is based on FPGAs. In the former architecture, the FPGA will execute the complex algorithms when required and remain in suspend mode when it is not needed. On the other hand, the latter serves to extend the capabilities of commercial sensor gateways by providing secure time-stamping of events. Drawing on these architectures, several designs are presented based on both the low-cost Spartan-6 and the low-power Artix-7 FPGAs. First, we added key negotiation capabilities to the IEEE 802.15.4 security suite based on Elliptic Curve Cryptography (ECC). This resulted in an accelerator for a sensor node that can be used as a separate coprocessor in an FPGA-based sensor node. Moreover, our accelerator behaves better in terms of speed and energy consumption than contemporary software solutions for sensor nodes such as the TinyECC and NanoECC libraries. Second, we proposed maximizing the utilization of the new DSP48E1 slice of the low power Artix-7 platform for replacing bit-wise logic operations of a wide range of cryptographic algorithms. As it turns out, it is possible to construct very compact architectures for the Authenticated-Encryption (AE) schemes Counter with CBC-MAC (CCM) and Galois/Counter Mode (GCM), compared to prior work based on reducing the Advanced Encryption Standard (AES).

Finally, a solution for adding time-stamping in a Wireless Body Area Network (WBAN) context purely based on FPGA is proposed. The system guarantees the chronological order of logged events sent by different sensors. Moreover, it allows to detect modification, deletion, and addition of logged data. Our results suggests that by maximizing the utilization of embedded resources of FPGAs e.g. DSP blocks, it is possible to reduce the implementation area of the design which can be crucial for selecting a target platform in lowbudget contexts. Moreover, the utilization of FPGAs as accelerators in sensor node architectures based on the combination of Microcontroller Unit (MCU) and FPGA suggests that improvements in speed and energy consumption can be achieved in comparison to software implementations. This architecture can be used as an alternative way of constructing sensor nodes in low-budget contexts where ASIC design of ultra-low power nodes is not an option. Moreover, the fact that novel FPGAs are equipped with more and more sensors and reconfiguration capabilities reflects that proactive strategies for counteracting physical attacks can be developed.

The promotors of the work are Prof. A. Touhafi & Prof. J. Cornelis.