Presenter

Ahmed Abdel-Hamid [Email]

Abstract

This dissertation introduced novel methods to introduce digital delay timing monitors to a standard HDL flow at RTL. The core patented method of this dissertation named ‘Blade’, demonstrated the automated ability of insertion of either monitor or knob with unlimited number and before synthesis. Moreover, the method illustrated demonstrated the ability to have a flexible communication scheme between either monitors or knobs with simple extensions to the literature available circuits. The communication scheme could be as simple as a scan-chain or as complex as a network on chip. As to prove the concept, we focused only on digital timing monitors, and scan-chain like communication scheme to implement and test the method.
The method evolved to a tangible tool that was successfully used in three ASIC chips: FlexFEC wireless 65nm chip of IMEC, and Tempo-32 triple fault tolerant design of the European Space Agency, and an Ultra Low Power Reconfigurable Processor for Biomedical Applications of Holst Center in the Netherlands. The thesis focus was mainly the FlexFEC chip to demonstrate the concept of the method. We have inserted 103 monitors to the design automatically before synthesis. Results have shown the methodology is functioning successfully, with major design issues of the monitor used.

Short CV

Master of Science in Embedded System Design, Universita della Svizzera Italiana, 2007