Presenter

Mr. Khaled Khalaf - ETRO, Vrije Universiteit Brussel and IMEC Leuven [Email]

Abstract

The insatiable need of consumers worldwide for higher data rates in wireless communication brings the frequencies of operation towards the millimeter wave spectrum (between 30 GHz and 300 GHz). Today’s wireless communication used in cell phones, tablets, laptops uses different communication standards that operate below 6 GHz. A few years ago, a frequency band between 57 GHz and 66 GHz has been allocated for wireless communication at data rates that exceed 1 Gbit per second. Before 2020, other frequency bands in the mm-Wave range will be used as well.
To allow wireless communication above 1 Gbit/s with mobile handsets, the power consumption of the transmit/receive circuitry needs to be kept low. Typically, the transmitter is responsible for the highest power consumption. This PhD. tackles the integrated circuit design of transmitters for communication in the 57-66 GHz frequency band. The implementation technology is downscaled CMOS, which allows for small form factors in combination with a low price when the chip is fabricated in high volumes.
The challenges of a 60 GHz transmitter are threefold: first, a power of more than 0 dBm needs to be delivered by the power amplifier (PA) that is at the output of the transmitter. This needs to be done at a sufficiently high efficiency. Next to the high efficiency, the transmitter needs to be sufficiently linear such that the information that is sent in the air by the transmitter does not get too much distorted. Thirdly, the high operating frequency, which can only be achieved if sufficiently downscaled CMOS is used, limits the design space and constrains the performance and the efficiency.
The first designs that have been realized in this PhD. are transmitters based on PAs operating in deep class AB to improve the operating efficiency. A 40nm low-power CMOS front-end comprising direct upconversion mixers and a three-stage class AB PA yields an output 1dB compression point of 10.2 dBm with an efficiency of 5.7% at a 5 dB backoff from this compression point. This efficiency is almost three times higher than an earlier realization in this technology that operated in class A. A second realization in this technology is a front-end that fits in a transmitter with four-way beamforming. This front-end uses a two-stage PA that can operate efficiently in class A and AB. The output 1dB compression point of the entire transmitter is 10.8 dBm in class A and 8 dBm in class AB. The efficiency at a 5 dB backoff from this compression point ranges from 4.9% (class A) to 7.4% (class AB). The third implementation in 28nm obtains compression values of 8.5 dBm and 10.2 dBm with 3.2% and 11.4% 5 dB backoff efficiency in class A and AB, respectively.
In an attempt to improve the efficiency at back-off, a polar transmit architecture has been explored. In this PhD. the first realization of such architecture at mm-Wave frequencies have been demonstrated. Two chips have been implemented in 40nm general-purpose CMOS with an average PA efficiency of 15.3% at a signal EVM of -23.6 dB allowing a QPSK signal with 3.5 Gbit/s raw datarate. The measurement results are promising and pave the way for further optimization of this architecture to achieve higher linearity targeting higher datarates at mm-Wave frequencies.

Short CV

Master in Electrical Engineering, TU Delft, 2010