Presenter

Mr Trong Huynh Bao - ETRO, Vrije Universiteit Brussel en IMEC [Email]

Abstract

For sub-20nm CMOS technology generations, conventional transistor and lithography scaling have hit significant difficulties. Other avenues such as alternative device architectures, asymmetric pitch scaling or emerging materials had to be exploited to achieve power/performance/area/cost (PPAC) scaling targets without shrinking design rules by the classical 0.7 factor. Today, technologists are facing increasingly complex choices which need to be evaluated from integration up to the circuit level. Therefore, Design-Technology Co-optimization (DTCO) has become a key methodology to enable CMOS downscaling. This Ph.D. develops a DTCO approach to the extension of CMOS in the 3rd dimension.
In a conventional 2D CMOS layout, the transistor gate length (Lg), sidewall spacer and source/drain contacts compete with each other, which limits contacted gate pitch scaling. This ultimately affects logic cell width scaling while routing congestion and accessibility limits the cell height. Looking towards technologies in the 5nm node and beyond, scalability of Lg of FinFET technology becomes questionable if the subthreshold slope and short channel effects (SCEs) need to be maintained. To overcome these challenges, a more disruptive architecture called vertical gate-all-around (GAA) transistor (VFET) is being proposed as a potential candidate to maintain CMOS scaling. Lg is now defined by the thickness of the metal gate and no longer limited by contacted gate pitch and source/drain contacts. In this work, maintaining Lg to 20 nm is sufficient to maintain VFET performance.
Digital standard cells form one of the critical building blocks of a modern system-on-chip (SoC). By using logic synthesis and automated place-and-route (APR) tools, most logic blocks can be realized with these standard cells. Therefore, area efficiency, power and timing of a SoC are strongly determined by the architectural choices of standard cell libraries. By using a representative critical path circuit composed of a NAND2 in a generic low power SoC, we show that the VFET-based circuit can be 40% more energy efficient than lateral FET (LFET) designs at iso-performance. At logic block level, a 32-bit multiplier implemented with the VFET-based standard-cell library can achieve a 19% area reduction.
The increasing transistor count at every technology node and parasitic resistance have also escalated the impact of RC delay in interconnects. Consequently, it is critical to investigate the consequence of different patterning options for interconnects. The results show that the 193i SAQP with positive tone process will require more than 4× in process margin and suffer a 50% loss in parametric yield. The impact of overlay error on LELE technology with EUV lithography (EUVL) become critical only when overlay variation is 6× higher than CD variation.
In many applications, the SRAMs occupies a large portion of a die and consumes most of the standby leakage current. Meanwhile, CMOS scaling has taken SRAMs into the nanoscale regime where it is difficult to simultaneously achieve the expected density, performance and energy constraints. Our results show that VFET bitcells are denser than LFET bitcells by 20-30%. The SRAM read stability (RSNM) is improved significantly by using the nanowire channel. For a 6𝜎𝜎 yield target and iso-area of SRAM bitcells, the Vmin of the VFET bitcell is 170 mV lower than LFET designs. Applying the proposed VT retargeting technique allows the VFET 122 bitcell to operate at 0.57 V without assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At iso-performance, the standby leakage of VFET bitcells is 2.6× lower than LFET bitcells.
To conclude, this thesis will explore different standard-cell architecture for VFETs, impact of patterning choices on circuit performance and SRAM optimizations to assess performance-power-area (PPA) trade-offs associated with each process integration choices. The thesis aims at bridging the circuit-process gap at an early stage of process development to offer an optimized solution for scaling CMOS technology in three dimensions.

Short CV

Master of Science Politecnico di Torino, Italy, 2012