Presenter

Mr Wagdy Gaber - ETRO, Vrije Universiteit Brussel and IMEC [Email]

Abstract

In the era of internet of things (IOT)s, machine to machine and 5th generation (5G) mobile communications, several hundred thousands of simultaneous connections with high data rate need to be supported by the wireless network. To support these insatiable demands of communications complexity, wide band width (BW), high linearity and high efficiency features are becoming indispensable for a modern radio-frequency (RF) transmitter (TX).

In addition, low fabrication cost of CMOS integrated solutions is a key driver in the wireless consumer market (smart phones, tablets and etc..). Modern CMOS technologies offer high level of integration, high speed logic and optimized power consumption for the digital processors in the wireless devices. Therefore, there is a strong need to integrate RF TXs with their power amplifiers (PA)s in the same CMOS chip. Exploiting the high speed switching of modern CMOS technologies in favor of modern communications requirements, in the state of art, a direct digital to RF modulator (DDRM) has appeared.

A proposed four-phase current-based IQ DDRM is the main contribution of the thesis. It features inherent current linearity, wide BW operation beside improved efficiency. However, the IQ DDRM faces three main challenges posed by modern communications standards: poor out of band (OOB) noise in frequency division duplex (FDD) systems, relatively low average efficiency with modern complex modulations and limited peak output power (Pout) capabilities due to limited supply voltage (VDD) of modern CMOS. To face these challenges, in this PhD, three different ideas are proposed with their fabricated prototypes.

First, an innovative concept of an IQ DDRM implemented in a FIR configuration is proposed to improve the IQ DDRM’s OOB noise. A healthy 22 dB improvement in the OOB noise has been measured at 0.9 GHz.

Second, to improve the average efficiency of a DDRM, a Doherty IQ DDRM is proposed: two IQ DDRMs are power combined in a Doherty-like configuration using two different and series on-chip transformers. Thanks to the proposed Doherty DDRM, at 𕒺 dB back-off, 12% drain efficiency improvement has been measured at 2.4 GHz.

Third, towards improving peak Pout and efficiency of an IQ DDRM in modern CMOS technologies with its limited VDD, a pseudo-differential stacked transistor is designed on top of an IQ DDRM in 28 nm bulk CMOS technology. Thanks to the proposed stacked IQ DDRM, operating VDD gets double which leads to a 6 dB more Pout. A peak Pout of 25 dBm with a 45% power added efficiency (PAE) is measured at 1 GHz. In addition, the stacked IQ DDRM achieves good linearity of a 3% rms error vector magnitude (EVM) when transmitting a 40MHz 64QAM WLAN signal at 12 dBm average Pout with peak Pout of 20.73 dBm.

Short CV

Master of Science, Alexandria University, Egypt, 2010