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%0 Conference Paper %A P. Renukaswamy %A N. Markulic %A S. Park %A A. Kankuppe Raghavendra Swamy %A Q. Shi %A P. Wambacq %A J. Craninckx %T A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth %B 2020 International Solid-State Circuits Conference %C San Francisco %I Institute of Electrical and Electronics Engineers ( IEEE ) %8 Feb. 2020 %P 3
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