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Conference Publication

%0 Conference Paper

%A A. Spagnolo

%A B. Verbruggen

%A S. D'amico

%A P. Wambacq

%T A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS

%B European Solid State Circuits Conference (ESSCIRC)

%I IEEE

%8 2014

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Current ETRO Authors

Prof. Piet Wambacq

+32 (0)16 281 218

pwambacq@etrovub.be

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