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Monolithically Integrated Detector/Receiver in standard CMOS Operating at 250 Mbit/s for low-cost Plastic Optical Fiber data links Host Publication: SPIE conference on Design Fabrication, and Characterization of Photonic Devices, vol 3896, pp 281-288 Authors: M. Kuijk, D. Coppée and R. Vounckx Publisher: SPIE Publication Year: 1999 Number of Pages: 8 ISBN: 0-8194-3498-1
Abstract: To solve the "lower frequency gain" that limits the speed of conventional CMOS detectors, we spatially modulate CMOS photo diode junctions. This gives a differential photodiode with a flat responsivity curve up to a DždB bit rate of more than 500 Mbit/s. Detector and circuitry (for receiver, digitizing, decoding etc), can now be combined on a single -low cost-CMOS chip for daracom applications. Here we report on the first integration of a receiver (including decision circuitry) with a 300 mu m diameter detector intended for use in plastic optical fiber (POF) links. The diameter of the detector allows to choose for large multimode POF cores (e.g. 250 mu m) and low precision mechanical connectors. The receiver circuit is fully differential from the detector onwards, for improved power supply rejection. A differential feedback mechanism filters out the DC-level. A final symmetric OTA converts the differential:signal to a single ended digital output. The total chip area including bonding pads is 440 mu m x 600 mu m The received optical power to obtain a BR of 10(Nj) (635 nm wavelength with PRBS 2(15)ǃ) is ᆥ.6 dBm (17.2 mu W) at a bit rate of 155 Mbit/s and similar to 12.2 dBm (60 mu W) at 250 Mbit/s bit rate. The chip dissipates only 25.3 mW at a 3.3V power supply. The bit rate is receiver limited. A design in a smaller feature size CMOS technology will show even better bit-rate and/or sensitivity performance. In conclusion, it is now possible to make detector/receivers combinations in standard CMOS lowering the overall cost of a POF data link system
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