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Device-, Circuit-Block-level evaluation of CFET in a 4 track library Host Publication: 39th Symposium on VLSI Technology, VLSI Technology 2019 Authors: P. Schuddinck, O. Zografos, P. Weckx, P. Matagne, S. Sarkar, Y. Sherazi, R. Baert, D. Jang, D. Yakimets, B. Parvais, D. Verkest and A. Mocuta Publisher: Institute of Electrical and Electronics Engineers Inc Publication Date: Jun. 2019
Abstract: The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2x higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET without the need to lower S/D contact resistivity down to 5eᆞOcm2 or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 N2 technologies. Keywords: CFET, scaling, S/D engineering, Pi-gate.
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