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B. Parvais, L. Peng, L. Teugels, E. Rosseel, A. Vandooren, J. Franco, A. Walke, V. Deshpande, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, E. Vecchio, T. Zheng, W. Vanherle, A. Hikavyy, G. Mannaert, B. T. Chan, R. Ritzenthaler, J. Mitard, L. Ragnarsson, N. Waldron, V. De Heyn, J. Boemmels, D. Mocuta and N. Collaert, “First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers,” in 64th Annual IEEE International Electron Devices Meeting, IEDM 2018, Institute of Electrical and Electronics Engineers Inc, Jan. 2019.

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Current ETRO Authors

Mr. Bertrand Parvais

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bparvais@etrovub.be

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