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A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS Host Publication: 2018 Symposia on VLSI Technology and Circuits Authors: N. Markulic, P. Renukaswamy, E. Martens, B. van Liempd, P. Wambacq and J. Craninckx UsePubPlace: Honolulu, HI, USA Publisher: 2018 IEEE Symposium on VLSI Circuits Publication Date: Oct. 2018 Number of Pages: 2
Abstract: We present a subsampling polar transmitter (SSPTX) in 28nm CMOS that consists of a low-noise phase modulating (PM) digital subsampling PLL and a harmonic rejection mixed (HRM) inverse-class-D (D- 1 ) digital power amplifier (DPA) for amplitude modulation (AM). The DPA is, unlike in a typical polar TX, placed within the PLL and the phase-error detection happens directly at the DPA output. The subsampling polar TX thus becomes sensitive not only to phase-errors, but also to modulation amplitude. That feature enables AM distortion to be detected and canceled digitally in the background while the transmitter operates normally. The chip operates from a 0.9V supply at 5.5GHz with 2.5MHz BW and 1024 QAM, consuming on average 46mW.
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