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Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication This publication appears in: IEEE JOURNAL OF SOLID-STATE CIRCUITS Authors: C. Tsai, Z. Zong, F. Pepe, G. Mangraviti, J. Craninckx and P. Wambacq Volume: 55 Issue: 7 Pages: 1854-1863 Publication Date: May. 2020
Abstract: This article analyses and demonstrates a 22.5㪳.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for millimeter-wave (mm-wave) communication. A discrete-time PLL model, together with theoretical transfer functions, gives insight on the functionality of the automatic bandwidth control, on the effect of the gear-shift algorithm for fast lock and on the different noise contributions. The proposed gear-shift algorithm scales up the PLL bandwidth for faster acquisition and orderly reduces it for jitter performance. The PLL contains a digitally controlled oscillator (DCO) based on transformer feedback with a tunable source-bridged capacitor, which allows for a low phase noise (PN) over a wide tuning range (FoM of -184 dBc/Hz and FoM T of -191 dBc/Hz) and for a fine frequency resolution. The PLL occupies 0.09-mm 2 core area and exhibits 220 fs rms jitter while consuming 25 mW, giving FoM RMS of -239 dB. Its frequency acquisition time improves from 780 to 45 µs with the gear-shift algorithm. For 60-GHz communication, with a frequency multiplication factor of 2.5, this PLL covers all six channels’ frequencies of IEEE닪.11ad, allows a transmitter (TX) error vector magnitude (EVM) down to -35.9 dB assuming a TX signal to the noise-plus-distortion ratio (SNDR) of 40 dB, and, thus, is capable of supporting 256 quadrature amplitude modulation (QAM).
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