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Power-performance trade-offs for Lateral NanoSheets on ultra-scaled standard cells Host Publication: 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 Authors: M. Garcia Bardon, Y. Sherazi, D. Jang, D. Yakimets, P. Schuddinck, R. Baert, H. Mertens, L. Mattii, B. Parvais, A. Mocuta and D. Verkest Publisher: Institute of Electrical and Electronics Engineers Inc Publication Date: Oct. 2018 Number of Pages: 2
Abstract: In this paper, the performance of standard cells scaled down to 4.5 metal tracks based on Lateral NanoSheets is investigated for 3nm technology node targets using relevant logic benchmarks and power-aware metrics. The cell layout and parasitics in 4.5T cells set strong constraints on the NanoSheets geometry. The optimized NanoSheets could still outperform FinFETs by 9 to 20% frequency depending on circuit context, reaching 3nm node targets. An extra 21% performance improvement is expected with device level boosters enablement.
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