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High-Level Cache Modelling for 2-D Discrete Wavelet Transform Implementations This publication appears in: Journal of VLSI Signal Processing Systems Authors: Y. Andreopoulos, P. Schelkens, P. 362, K. Masselos and J. Cornelis Volume: 34 Issue: 3 Pages: 209-226 Publication Date: Jul. 2003
Abstract: The main implementations of the 2-D binary-tree discrete wavelet decomposition are theoretically analyzed and compared with respect to data-cache performance on instruction-set processor-based realizations. These implementations include various image-scanning techniques, from the classical row-column approach to the block-based and line-based methods, which are proposed in the framework of multimedia-coding standards. Analytical parameterized equations for the prediction of data-cache misses under general realistic assumptions are proposed. The accuracy and the consistency of the theory are verified through simulations on test platforms and a comparison is made with the results from a real platform.
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