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Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements This publication appears in: Computer Systems: Architectures, Modeling and Simulation Authors: P. Schelkens, F. Verdicchio, H. Devos, H. Eeckhaut and D. Stroobandt Volume: 3133 Pages: 203-212 Publication Year: 2004
Abstract: Multimedia applications emerge on portable devices everywhere. These applications typically have a number of stringent requirements: (i) a high amount of computational power together with real-time performance and (ii) the flexibility to modify the application or the characteristics of the application at will. The performance requirements often drive the design towards a hardware implementation while the flexibility requirement is better served by a software implementation. In this paper we try to reconcile these two requirements by using an FPGA to implement the performance critical parts of a scalable wavelet video decoder. Through analytical means we first explore the performance and resource requirements. We find that modern FPGAs offer enough computational power to obtain real-time performance of the decoder, but that reaching the necessary memory bandwidth will be a challenge during this design.
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