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CMOS Receiver Array with 100 channels on 1 mm2 chip area based on Self-Calibrating Self-Regenerative Sense-Amplifiers Operating at 200 Mbit/s/channel Host Publication: OPTOELECTRONIC INTERCONNECTS VII PHOTONICS PACKAGING AND INTEGRATION II Authors: M. Kuijk, D. Coppée, J. Genoe and R. Vounckx Publisher: SPIE Publication Date: Jan. 2000 Number of Pages: 8 ISBN: 0-8194-3569-4
Abstract: Parallel optical interconnects may become the communication method of choice to achieve future high bandwidth data transfer between chips or MCM's. For this purpose, an integrated CMOS detector approach is favorable at the light-reception side, so Flip-chip of detectors is no longer required. In this paper we present an integrated differential CMOS detector layout which gives a flat frequency response of 0.1A/W with a DždB bit rate over 450Mbit/s/ch (wavelength of 860nm) in standard 0.6 mu technology. The detector works following the Spatially Modulated Light detector (SML-detector) principle. Based on this SML-detector we fabricated a dense detector/receiver array consisting of 100 channels on one square mm Si area in 0.6 mu standard CMOS. The detector area is 50x50 mu(2). The detector signal is amplified and latched by a self-regenerative sense-amplifier, which is self-calibrating for increased array homogeneity and receiver yield. The power consumption per receiver channel is as low as 1.1mW and the received light power at 200Mbit/s is 25.1 mu W (at a BER
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