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A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS This publication appears in: IEEE JOURNAL OF SOLID-STATE CIRCUITS Authors: V. Szortyka, Q. Shi, K. Raczkowski, B. Parvais, M. Kuijk and P. Wambacq Volume: 50 Issue: 9 Pages: 2025-2036 Publication Date: Jun. 2015
Abstract: A 60 GHz sub-sampling PLL implemented in 40 nm CMOS is presented in this paper. The sub-sampling phase detector (SSPD) runs at 30 GHz after an inductively-peaked static divide-by-two. Thanks to the lower frequency of operation, the effect of non-zero sampling aperture of the switch is minimized. A dummy divider of the quadrature PLL is utilized for the sub-sampling loop to avoid extra loading in the 60 GHz path. A 53.8ᇓ.3 GHz QVCO uses super-harmonic coupling at 120 GHz for relaxed headroom at a 0.9 V supply and achieves a free-running phase noise down to ᇲ.5 dBc/Hz at 1 MHz offset. The millimeter-wave sub-sampling PLL achieves an RMS jitter, integrated from 1 kHz to 100 MHz, of 200 fs at a power consumption of 42 mW, compared to 210 fs for the PFD/CP PLL at 75 mW. Reference spurs in both modes are below ᆼ dBc.
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