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A 42mW 230fs-Jitter Sub-sampling 60GHz PLL in 40nm CMOS Host Publication: 2014 IEEE International Solid-State Circuits Conference, ISSCC Authors: V. Szortyka, Q. Shi, K. Raczkowski, B. Parvais, M. Kuijk and P. Wambacq Publication Date: Feb. 2014
Abstract: this paper presents the first mm-Wave PLL utilizing a subsampling
phase detector instead of a classical divider chain. Implemented in 40nm CMOS, the PLL has a jitter as low
as 230fs for a power consumption of 42mW.
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