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A 2.6 mW 6b 2.2GS/S 4-times Interleaved Fully Dynamic Pipelined ADC in 40 nm Digital CMOS Host Publication: IEEE International Solid-State Circuits Conference (ISSCC) Authors: B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq and G. Van Der Plas Publisher: IEEE Publication Date: Feb. 2010 Number of Pages: 2 ISBN: 978-1-4244-6033-5
Abstract: A 2.2 GS/S 4*-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. Threshold calibration corrects for amplifier and comparator imperfections and 31.6 dB SNDR is achieved with 2 GHz ERBW for 2.6 mW power consumption
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