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Wafer-level package interconnect options This publication appears in: IEEE Transactions on very large scale integration (VLSI) Systems Authors: J. Balachandran, S. Brebels, G. Carchon, M. Kuijk, W. De Raedt, B. Nauwelaers and E. Beyne Volume: 14 Issue: 6 Pages: 654-659 Publication Date: Jun. 2006
Abstract: As integrated circuit technology enters the nanometer era, global interconnects are becoming a bottleneck for overall chip performance. In this paper, we show that wafer-level package interconnects are an effective alternative to conventional on-chip global wires. These interconnects behave as LC transmission lines and can be exploited for their near speed of tight transmission and low attenuation characteristics. We compare performance measures such as bandwidth, bandwidth density, latency, and power consumption of the package-level transmission lines with conventional on-chip global interconnects for different International Technology Roadmap for Semiconductors (ITRS) technology nodes. Based on these results, we show that package-level interconnects are well suited for power demanding low-latency applications. We also analyze different interconnect options such as memory buses, long inter tile interconnects, clock, and power distribution
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