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Vertical device architecture for 5nm and beyond: device & circuit implications Host Publication: 2015 Symposium on VLSI Technology and Circuits Authors: A. Thean, D. Yakimets, T. Huynh Bao, P. Schuddinck, S. Sakhare, M. Garcia Bardon, A. Sibaja-Hernandez, I. Ciofi, G. Eneman, A. Veloso, P. Raghavan, A. Mercha, Z. Tokei, D. Verkest, P. Wambacq, K. De Meyer and N. Collaert Publisher: IEEE Publication Year: 2015
Abstract: Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.
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