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A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL Host Publication: 2016 IEEE International Solid-State Circuits Conference (ISSCC) Authors: N. Markulic, K. Raczkowski, E. Martens, P. Paro, B. Hershberg, P. Wambacq and J. Craninckx Publisher: IEEE Publication Date: Jan. 2016 Number of Pages: 2 ISBN: 978-1-4673-9466-6
Abstract: The two-point injection scheme has proven to be an effective technique for overcoming the problem of PLL bandwidth limitations during wideband polar phase modulation. The quality of the phase-modulated signal, typically expressed in terms of error-vector magnitude (EVM), still remains limited by the PLL phase-noise, gain mismatch between the two injection paths and linearity of the digital-to-modulated phase conversion. We present a phase modulator that makes use of an analog, fractional-N, digital-to-time-converter (DTC)-based subsampling PLL that achieves ᆹ.4dB EVM around a 10.24GHz fractional carrier during 10Mb/s GMSK modulation. The subsampling PLL architecture uses no power-consuming divider and allows wide PLL bandwidth (because of its high phase-error detection gain) for optimal VCO noise suppression. The VCO has a secondary, digitally controlled capacitor bank (modulating DAC) used during two-point modulation. The gain errors and nonlinearities in the digital-to-modulated phase conversion are automatically background-calibrated in both injection points: in the phase-error detection path (where nonlinearity is dominated by the DTC INL) and in the VCO modulating capacitor bank (where nonlinearity is dominated by capacitor mismatch and nonlinear capacitance-to-frequency conversion).
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