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A transmitter with 10b 128MS/s incremental-charge-based DAC achieving -155dBc/Hz out-of-band noise Host Publication: 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers Authors: P. Paro, P. Wambacq, M. Ingels and J. Craninckx Publication Date: Feb. 2015 Number of Pages: 2
Abstract: Driven by increasing data-rates, advanced mobile communication systems impose stringent requirements on every transmitter design aspect. Especially when the inter-stage SAW filter is removed, FDD operation using high-order modulation schemes (as in e.g. WCDMA, LTE) demands both remarkable noise performance and linearity, which is difficult to achieve without sacrificing power consumption. On the other hand, the increased switching speed of nanoscale MOS transistors has enabled the implementation of various digital-intensive TX architectures [1LJ], that improved system robustness and reduced power and area consumption even in face of decreased supply voltages. However, in these cases reconstruction filtering is hindered by direct digital-to-RF conversion, leading to increased quantization noise and strong sampling aliases. Often addressed by increasing the converter resolution [2,3,4,6] and/or sampling frequency [2], these solutions typically become rather costly and directly affect the overall power consumption. This work introduces a TX architecture that innovates by operating in the charge domain. Its incremental — rather than absolute — signaling improves both quantization noise performance and power consumption. Using a 128MS/S 10b DAC configuration, it achieves -155dBc/Hz at 45MHz offset from a 1GHz modulated carrier, with intrinsic sampling alias attenuation. External Link.
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