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Signal Processing Challenges for Emerging Digital Intensive and Digitally Assisted Transceivers with Deeply Scaled Technology Host Publication: 2013 IEEE Workshop on Signal Processing Systems (SiPS 2013) Authors: M. Li, K. Khalaf, C. Li, V. Vidojkovic, M. Ingels, A. Bourdoux, P. Wambacq, J. Craninckx and L. Van Der Perre Publisher: IEEE Publication Date: Oct. 2014 Number of Pages: 6 ISBN: 9781467362368
Abstract: Mainstream foundries are leaping toward 14nm node and beyond. Although aggressive scaling can substantially improve digital circuit, it is very controversial for analog circuit. However, analog circuit still has to follow the scaling trend because a single chip integration offers key commercial
advantages. To optimally achieve the best performance/power/cost tradeoff with deeply scaled technology
nodes, there is a clear trend and paradigm shift towards digital intensive and digitally assisted transceivers. Successes of such transceivers have been proven for individual transceiver components and narrow band systems. When targeting emerging communication standards, higher carrier frequencies, further technology scaling and reconfigurable radios, required signal processing design and implementation are orders of magnitudes more challenging but potential gains are promising. Illustrated with a variety of transceivers representing emerging architectures designed for different subLjGhz and 60Ghz communication systems, we will depict key challenges that we experienced in our design and optimization process with 40nm and 28nm technology nodes. External Link.
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