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A Digitally Modulated 60GHz Polar Transmitter in 40nm CMOS Host Publication: 2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Authors: K. Khalaf, V. Vidojkovic, K. Vaesen, J. R. Long, W. Van Thillo and P. Wambacq Publisher: IEEE Publication Date: Jun. 2014 Number of Pages: 4 ISBN: 978-1-4799-3862-9
Abstract: A 60GHz polar Tx prototype implemented in 40nm CMOS includes a two-stage PA with an RF-DAC, an I-Q upconversion mixer, a 60GHz LO hybrid and a digital synchronization interface. Saturated output power is approx. 10dBm, while RF output and baseband input bandwidths are 9GHz and 1.2GHz, respectively. The linear RF-DAC resolution is 5 bits. EVM degradation and spectral mask out-of-band distortion appear at input powers higher than 6dB above PǃdB. EVM is ᆧdB and ᆤdB at full rate, and ᆭ.5dB and ᆪdB at reduced rates for QPSK and 16-QAM signals, respectively. The Tx consumes 75mW from 0.9V, and the core occupies 0.18mm2 of the 2.38mm2 testchip. External Link.
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