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Frequency Enhancement of a 40-nm CMOS Static Frequency Divider by Negative Capacitance Host Publication: Microwave Integrated Circuits Conference (EuMIC), 2013 European Authors: V. Issakov, G. Mangraviti, V. Szortyka, V. Vidojkovic, G. Vandersteen and P. Wambacq Publication Date: Oct. 2013 Number of Pages: 4
Abstract: This paper presents a flip-flop based static current-mode logic (CML) frequency divider in CMOS using negative capacitance to enhance the performance. We show that thanks to the differential negative capacitance it is possible to compensate partially for the parasitic capacitance at sensitive nodes in the divider. This improves the divider's sensitivity at higher frequencies and increases its self-oscillation frequency (SOF). This is achieved simply by means of a minor modification of the latch, without the use of bulky inductors. In order to confirm this effect in measurement, we have realized two static 2:1 divider cells - a classical one for benchmarking and another one implemented with the proposed modification. For a fair comparison, both circuits are biased identically and use equal device sizes. The circuits have been realized in 40 nm low-power (LP) digital CMOS technology. Measurements show that for input levels below Lj dBmthe proposed divider has a better sensitivity at higher frequencies, thus extending the upper limit of the operating frequency range by up to 1.4 GHz. Both circuits consume 3.3 mA from a single 1.1 V supply.
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