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Impact of multi-gate device architectures on digital and analog circuits and its implications on system-on-chip technologies Host Publication: 2013 IEEE International Electron Devices Meeting Authors: A. Thean, P. Wambacq, J. Lee, M. Cho, A. Veloso, Y. Sasaki, T. Chiarella, K. Miyaguchi, B. Parvais, M. Garcia Bardon, P. Schuddinck, M. Kim, N. Horiguchi, M. Dehan, A. Mercha, G. Van Der Plas, N. Collaert and D. Verkest Publisher: IEEE Publication Year: 2013
Abstract: Abstract:This paper reviews some important process aspects of aggressively downscaled FinFET technologies and their implications on digital and analog figures of merits (FOMs). The need to downscale device architectures to enhance digital transistor electrostatics and circuit density led to influences in parasitics, variability, and noise, which impact analog FOMs. Therefore, it is important to understand the trade-offs due to the new devices and the upcoming process solutions to address them. Process features, variability and parasitics relevant to 14nm and beyond FinFET will be reviewed and their System-On-Chip (SOC) implications will be discussed.
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