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A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range Host Publication: 2012 IEEE International Solid-State Circuits Conference (ISSCC) Authors: B. Malki, T. Yamamoto, B. Verbruggen, P. Wambacq and J. Craninckx UsePubPlace: St. Louis, Missouri Publisher: IEEE Publication Date: Feb. 2012 Number of Pages: 2 ISBN: 978-1-4673-0373-6
Abstract: This paper presents a charge-domain SAR ADC which integrates the current of a variable-gain transconductor on its sampling capacitor, rather than being driven by a power hungry voltage buffer. The sampling circuit uses nonlinear MOS capacitors for passive amplification, without compromising linearity. The prototype in 40nm LP CMOS consists of a 1.1ᆥ.6mS transconductor, combined with a 10b 0ᇤMS/s charge-sharing SAR ADC. It achieves 70 dB DR while consuming less than 5.45mA from a 1.1V supply. External Link.
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