|
A 40 nm LP CMOS PLL for high-speed mm-wave communication Host Publication: Proceedings of the ESSCIRCཆ conference, Seville, 13-17 Sept. 2010 Authors: B. Parvais, K. Scheir, V. Vidojkovic, R. Vandebriel, G. Vandersteen, C. Soens and P. Wambacq Publication Date: Sep. 2010 Number of Pages: 1
Abstract: A phase-locked loop (PLL) that can be used in a zero-IF radio architecture with beamforming for AV-OFDM with 16-QAM modulation is demonstrated for the first time in 40 nm LP CMOS technology. This type II integer-N PLL of order four includes an injection-locked divide-bydž prescaler and two quadrature series-coupled VCOs, operating in 63ᇚ GHz and 72ᇥ GHz frequency bands. It achieves ᇩ dBc/Hz in-band phase noise at 64 GHz, corresponding to ᆧ.4 dBc integrated phase noise, while consuming 60 mA from a 1.1 V supply.
|
