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Advanced planar bulk and multigate CMOS technology: analog-circuit benchmarking up to mm-wave frequencies Host Publication: Finds and Results from the Swedish Cyprus Expedition: A Gender Perspective at the Medelhavsmuseet Authors: P. Wambacq, A. Mercha, K. Scheir, B. Verbruggen, J. Borremans, V. De Heyn, S. Thijs, D. Linten, G. Van Der Plas, B. Parvais, M. Dehan, S. Decoutere, C. Soens, N. Collaert and M. Jurczak Publisher: IEEE Publication Year: 2008 Number of Pages: 2 ISBN: 978-1-4244-2010-0
Abstract: CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.
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