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A 150 MS/s 133 \muW 7 bit ADC in 90 nm Digital CMOS This publication appears in: IEEE JOURNAL OF SOLID-STATE CIRCUITS Authors: G. Van Der Plas and B. Verbruggen Volume: 43 Issue: 12 Pages: 2631-2640 Publication Date: Dec. 2008
Abstract: In recent years the energy efficiency of A/D converters has been improved significantly. Only 5 years ago [3] an energy efficiency of 1 pJ/conversion step was considered state-of-the-art. Now power efficiencies are reported in fJ/conversion step. In this paper two new converter techniques are presented that further improve upon reported energy efficiencies of A/D converters. The first technique implements the quantization with a comparator-based asynchronous binary search (CABS). The second technique implements the SAR control algorithm on the comparators (SAR-CC) that are also used to do the quantization. Both these techniques have been applied in a fully dynamic 7 bit A/D converter that uses a two-step lb coarse and 6b fine architecture [2]. The 1b coarse converter is implemented using the SAR-CC principle, the 6b fine converter is implemented using the CABS principle. The 7 bit prototype implementation in 90 nm digital CMOS on a 1 V supply achieves 6.4ENOB, 40 dB SNDR at 150 MS/s consuming 133 muW giving 10 fJ/conversion step energy efficiency (FOM). A second prototype implementing a stand-alone 6b CABS converter (the sub-A/D converter of the 7 bit converter) achieves 32 dB SNDR at 250 MS/s with 140 muW of power consumption, which results in a FOM of 15 fJ/conversion step.
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