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A 150MS/s 133uW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC Host Publication: 2008 IEEE International Solid-State Circuits Conference (ISSCC) Authors: G. Van Der Plas and B. Verbruggen UsePubPlace: Lewiston, Maine Publisher: IEEE Publication Date: Feb. 2008 Number of Pages: 2 ISBN: 978-1-4244-2010-0
Abstract: A fully dynamic 7b ADC uses a 2-step 1b-coarse 6b-fine architecture. The 6b-fine converter is implemented using a comparator-based asynchronous binary-search architecture. The prototype implementation in 90nm digital CMOS with a 1V supply achieves 6.4 ENOB and 40dB SNDR (over the whole Nyquist band) at 150MS/s, yielding a 10fJ/conversion step energy efficiency.
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