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Field-programmable gate array implementation of an all-digital IEEE 802.15.4-compliant transceiver This publication appears in: International Journal of Electronics Authors: G. Cornetta and A. Touhafi Volume: 97 Issue: 12 Pages: 1361-1378 Publication Date: Mar. 2010
Abstract: An architecture for a low-cost, low-complexity digital transceiver is presented. The proposed architecture targets the IEEE802.15.4 standard for wireless short-range personal area networks (WPANs) and has been implemented as synthesisableVHDL register transfer level (RTL) description. The system has been evaluated and tested using a Xilinx 90 nm VirtexdžFPGA as the target technology. Bit Error Rate (BER) and Error Vector Magnitude (EVM) has been used as the figures ofmerit for modem performance. Simulations show that the recommended minimum BER is achieved with at Eb/N0 = 8.7 dB,whereas the EVM is 19.5%. The implemented device occupies 10% of the target FPGA and has a normalised maximum power consumption of 44mW in transmit mode and 53 mW in receive mode.
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