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A 21-dBm I/Q Digital Transmitter Using Stacked Output Stage in 28-nm Bulk CMOS Technology This publication appears in: IEEE Transactions on Microwave Theory and Techniques Authors: W. Gaber, P. Wambacq, J. Craninckx and M. Ingels Volume: 65 Issue: 11 Pages: 4744-4757 Publication Date: Jun. 2017
Abstract: This paper proposes the use of a high-power stacked output stage for a current-based in-phase/quadrature (I/Q) direct digital to RF modulator (DDRM) in bulk CMOS. The main nonlinearities associated with implementing the stacked transistor on top of the I/Q DDRM are easily compensated by a simple 2-D digital predistortion. A prototype implemented in 28-nm bulk CMOS achieves a saturated output power (P SAT ) of 25 dBm and a peak output power (P out ) of 21 dBm at 1-GHz carrier frequency ( f c ). Their corresponding efficiencies are 45% power added efficiency and 33% system efficiency (? sys ), respectively. In addition, it achieves 11.5% ? sys with a ᆲ.5-dB error vector magnitude when transmitting a 40-MHz 64 quadrature amplitude modulation wireless local area network (WLAN) signal. The WLAN signal is transmitted at 12-dBm average P out , and at 1-GHz f c with 8.73-dB peak to average power ratio (peak Pout of 20.73 dBm).
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