A mobile communication unit of the future will require a Software-Defined Radio (SDR) platform. This platform consists of an SDR Front-End integrated together with a baseband engine for digital signal processing in an RF System-on-Chip, in a nanoscale digital CMOS. This platform ideally enables to connect to any possible protocol.

Every transceiver has a receiver chain, a transmit chain and a system for local oscillator generation, typically implemented in a phase-locked loop (PLL). The last part is the focus of this PhD. It is the goal to bring significant new contributions to the state of the art in PLL design for the SDR systems.

Focus of this PhD is the phase-locked loop (PLL) for the local oscillator generation in SDR systems. Based on good system knowledge of all the different requirements of the communication systems envisioned, with access to advanced CMOS process technologies for prototype implementations, new PLL architectures and circuits are studied and developed to bring solutions that contribute to the state of the art in this field.