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3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability Host Publication: 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 Authors: B. Parvais, L. Peng, L. Teugels, E. Rosseel, A. Vandooren, J. Franco, A. Walke, V. Desphande, F. M. Bufler, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, G. Verbinnen, E. Vecchio, T. Zheng, W. Vanherle, A. Hikavyy, B. T. Chan, R. Ritzenthaler, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, N. Waldron, V. De Heyn, D. Mocuta and N. Collaert Publisher: Institute of Electrical and Electronics Engineers Inc Publication Date: Oct. 2018 Number of Pages: 2
Abstract: 3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k /metal replacement gate and low temperature Si:P and SiGe:B 60% raised SD for NMOS and PMOS respectively. Device matching, analog and RF performance of the top tier devices are in-line with state-of-the-art Si technology processed at high temperature (>1000°C). The top Si layer is transferred on CMOS planar bulk wafers with W metalǃ interconnects, using a SiCN to SiCN direct wafer bonding.
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