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Trap-aware compact modeling and power-performance assessment of III-V tunnel FET Host Publication: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 Authors: Y. Xiang, D. Yakimets, s. sant, E. Memisevic, m. garcia bardon, A. S. Verhulst, B. Parvais, A. Schenk, L. Erik Wernersson and G. Groeseneken Publisher: Institute of Electrical and Electronics Engineers Inc Publication Date: Feb. 2019 Number of Pages: 3
Abstract: We report, for the first time, on a SPICE simulation study of the circuit-level power-performance impact of device traps in a state-of-the-art III-V heterojunction tunnel FET (TFET). First, the individual parasitic effects of junction bulk traps and oxide interface traps are incorporated in a compact model and validated against measurement-calibrated TCAD data, where we propose an analytical formulation for trap-assisted tunneling at the heterojunction and account for the oxide interface charge with a look-up table. Then, the model is used in SPICE simulations on a ring oscillator test bench to predict the impact of traps on logic circuits. It is found that bulk and oxide traps in TFET together cause up to ~5x iso-frequency energy penalty in the desired low-supply-voltage domain (0.50 V), of which oxide traps dominate at high switching activity while bulk and oxide traps contribute comparably when switching is less active. This study quantitatively suggests that trap reduction is the key to the enablement of the full benefit of TFET.
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