|
|
Y. Xiang, D. Yakimets, s. sant, E. Memisevic, m. garcia bardon, A. S. Verhulst, B. Parvais, A. Schenk, L. Erik Wernersson and G. Groeseneken, “Trap-aware compact modeling and power-performance assessment of III-V tunnel FET,” in 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Institute of Electrical and Electronics Engineers Inc, Feb. 2019, pp. 3.
|
|
