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Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM Host Publication: 2015 International Conference on IC Design & Technology (ICICDT) Authors: T. Huynh Bao, S. Sakhare, D. Yakimets, A. Mercha, D. Verkest, A. Thean and P. Wambacq Publisher: IEEE Publication Date: Jun. 2015 Number of Pages: 4
Abstract: This paper presents a comprehensive benchmarking and co-optimization of 6T SRAM bitcells designed with 5nm vertical and lateral gate-all-around nanowire FET technology for the first time. A variety of 6T SRAM bitcells configurations combined with different device integration scenarios will be discussed. Our results show that an ultra-dense SRAM bitcell (0.01 um2) can be achieved with vertical FET architecture. The bitcell designed with vertical FET are preferably targeted for low power applications while the lateral FET-based SRAM bitcells could provide 4.5x higher in performance, but resulting in a penalty of 17x increasing in the leakage current compared to the vertical designs. A Vmin of 0.45 V could be obtained for 122 SRAM bitcells implemented with vertical devices.
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