|
|
T. Huynh Bao, S. Sakhare, D. Yakimets, A. Mercha, D. Verkest, A. Thean and P. Wambacq, “Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM,” in 2015 International Conference on IC Design & Technology (ICICDT), IEEE, Jun. 2015, pp. 4.
|
|
