CMOS downscaling keeps on continuing, despite the many rumours about a slowdown of Moore's law. For example, research at imec considers CMOS generations below 10nm. Of course, this scaling rush becomes increasingly more difficult and expensive. The high price rules out many applications. However, for applications with mass-market potential the large quantities of chips will provide a cost advantage for very downscaled CMOS.

Typical chips that will be made in CMOS generations below 10nm will be complex digital systems on chip. In such systems, although digital in nature, a lot of analog supporting circuits are needed, for example for the power management, thermal management, interfacing with the outside world, clock generation, ...

Hence it is important to know the performance of analog circuits in downscaled CMOS and to study effects that can influence their performance, such as variability, high-frequency behavior, 1/f noise and random telegraph noise, ...

This PhD. research domain is performed in close collaboration with imec, which provides devices, models, know-how on the advanced CMOS generations.