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Journal Publications

2020

P. Renukaswamy, N. Markulic, P. Wambacq and J. Craninckx, “A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/µs Slope and 1.2-GHz Chirp-Bandwidth,” IEEE Journal of Solid - State Circuits, vol. 2020, pp. 14, Sep. 2020.

2019

N. Markulic, P. Renukaswamy, E. Martens, B. Van Liempd, P. Wambacq and J. Craninckx, “A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With-41.3-dB EVM at 1024 QAM in 28-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 54, no. 4, pp. 1059-1073, Apr. 2019.

Conference Publications

2020

P. Renukaswamy, N. Markulic, S. Park, A. Kankuppe Raghavendra Swamy, Q. Shi, P. Wambacq and J. Craninckx, “A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth,” in 2020 International Solid-State Circuits Conference, San Francisco: Institute of Electrical and Electronics Engineers ( IEEE ), Feb. 2020, pp. 3.

2018

N. Markulic, P. Renukaswamy, E. Martens, B. van Liempd, P. Wambacq and J. Craninckx, “A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS,” in 2018 Symposia on VLSI Technology and Circuits, Honolulu, HI, USA: 2018 IEEE Symposium on VLSI Circuits, Oct. 2018, pp. 2.

2016

N. Markulic, K. Raczkowski, E. Martens, P. Paro, B. Hershberg, P. Wambacq and J. Craninckx, “A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL,” in 2016 IEEE International Solid-State Circuits Conference (ISSCC), IEEE, Jan. 2016, pp. 2.

N. Markulic, K. Raczkowski, P. Wambacq and J. Craninckx, “A Fractional-n subsampling PLL based on a digital-to-time converter,” in Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2016 39th International Convention on, Jul. 2016.

2014

N. Markulic, K. Raczkowski, P. Wambacq and J. Craninckx, “A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS,” in 40th European Solid-State Circuit Conference, IEEE, Sep. 2014, pp. 4.

K. Raczkowski, N. Markulic, B. Hershberg, J. Van Driessche and J. Craninckx, “A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter,” in 2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), IEEE, 2014, pp. 4.

Other Publications

2016

N. Markulic, K. Raczkowski, E. Martens, P. Paro, B. Hershberg, P. Wambacq and J. Craninckx, “A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Oct. 2016.

2015

K. Raczkowski, N. Markulic, B. Hershberg and J. Craninckx, “A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Mar. 2015.