Click here for this list in IEEE format.

Journal Publications

2020

“A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/µs Slope and 1.2-GHz Chirp-Bandwidth”, in IEEE Journal of Solid - State Circuits

2019

“A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With-41.3-dB EVM at 1024 QAM in 28-nm CMOS”, in IEEE Journal of Solid-State Circuits

Conference Publications

2020

“A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth”, in 2020 International Solid-State Circuits Conference

2018

“A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS”, in 2018 Symposia on VLSI Technology and Circuits

2016

“A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL”, in 2016 IEEE International Solid-State Circuits Conference (ISSCC)

“A Fractional-n subsampling PLL based on a digital-to-time converter”, in Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2016 39th International Convention on

2014

“A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS”, in 40th European Solid-State Circuit Conference

“A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter”, in 2014 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

Other Publications

2016

“A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation”, in IEEE JOURNAL OF SOLID-STATE CIRCUITS

2015

“A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter”, in IEEE JOURNAL OF SOLID-STATE CIRCUITS